History of Supercomputing, tell me if this format caused you any problems.

[David Farber <farber () central cis upenn edu>]

This document is a timeline of major developments in parallel computing. It
will eventually appear as part of a textbook on parallel programming, but
will also be separately published. All contributions and corrections are
welcomed, and should be sent to welcomed, and should be sent to gregw () cs anu edu au. (Please note that
actual entries are more likely to be followed up than comments of the form
"You should include something about system X -- I think there was an
article about it in CACM a few years ago, or maybe one of the IEEE
journals.") 

The persons listed below have contributed or corrected articles; I am
particularly grateful to Michael Wolfe, whose generous early assistance got
this off the ground, and to Eugene Miya, who provided many useful pointers.
I would also like to thank Andy Ben-Dyke and Graem Ringwood, who are
compiling entries on parallel functional and parallel logic programming
respectively for inclusion in the next release. 

TA      Tamir Azaz      tamir () meiko co uk
ADBD Andy Ben-Dyke      adb () cs bham ac uk
JB      John Bennett    jbennett () ncube com
EAB     Edward Bertsch  eab () msc edu
BMB     Bruce Boghosian bmb () think com
BRC     Brad Carlile    bradc () cray com
WD      Bill Dally      billd () ai mit edu
VDR     Vibha Dixit-Radiya      radiya-v () cis ohio-state edu
JD      Jack Dongarra   dongarra () cs utk edu
JF      John Feo        feo () diego llnl gov
JMF     Jim Flemming    flemming () vino enet dec com
WH      Willi Hasselbring       willi () informatik uni-essen de
RWH     Roger Hockney   RWH     Roger Hockney   rwh@pac,soton.ac.uk
RNI     Roland Ibbett   r.n.ibbett () ed ac uk
RJ      Rick Johnson    rickj () ssd intel com
LSK     Larry Kaplan    lkaplan () ultra tera com
AK      Alan Karp       karp () hplahk hpl hp com
HGK     Harwood Kolsky  harwood () cse ucsc edu
VK      Venkata Konda   vkonda () ncube com
HL      Hwa Lai hwal () fai com
CEL     Charles E. Leiserson cel () theory lcs mit edu
TL      Tom Lovett      tdl () sequent com
BM      Barry Margolin  barmar () think com
LFM     Larry Meadows   lfm () pgroup com
ENM     Eugene Miya     eugene () wilbur nas nasa gov
YO      Yoshio Oyanagi  oyanagi () is s u-tokyo ac jp
GP      George Paul     gp1 () watson ibm com
SCP     Stephen C. Perrenod     perrenod () renaissance cray com
RR      Robert Rau      rau () hplabs hpl hp com
JRR     James R. Reinders       reinders () ssd intel com
PR      Paul Repacholi  zrepachol () cc curtin edu au
ER      Erwin Reyzl     erwin.reyzl () zfe siemens de
MS      Matthias Schumann       schumann () informatik tu-muenchen de
MCS     Markus Schwehm  schwehm () immd7 informatik uni-erlangen de
DHS     Dave Shaver     shaver () convex com
RS      Roger Shepherd  roger () inmos co uk
MKS     Mark Smotherman mark () cs clemson edu
DS      Douglas E. Solomon      doug () sgi com
HSS     Harold Stone    hstone () sunset ee cornell edu
PDT     Philip Tannenbaum       b47tbaum () sx iah nec com
PGW     Paul Whiting    pgw () mel dit csiro au
GVW     Greg Wilson     gvw () epcc ed ac uk
MW      Mike Wolfe      mwolfe () cse ogi edu
HZ      Hans Zima       zima () icase edu

========1955========

IBM introduces the 704. Principal architect was Gene Amdahl; it was the
first commercial machine with floating-point hardware (capable of
approximately 5 kFLOPS). (GP: IBM, 704, Amdahl) 

========1956========

IBM starts 7030 project (known as STRETCH), with the goal of producing a
machine with 100 times the performance of the IBM 704, initiated by Atomic
Energy Commission at Los Alamos. (MW,HGK: IBM, STRETCH) 

Atlas project begins at University of Manchester; principal architect is
Tom Kilburn. (RNI: Atlas)

========1958========

Bull of France announces the Gamma 60 with multiple function units and fork
and join operations in its instruction set; 19 are later built. (MKS: Bull,
Gamma 60)

========1959========

IBM delivers first STRETCH computer. Only seven are ever built, but much of
the techology re-surfaces in the later IBM 7090 and 7094. (MW,HGK: IBM,
STRETCH)

========1960========

Control Data starts development of CDC 6600. (MW: CDC, Cray, CDC 6600)

========1962========

C. A. Petri describes Petri Nets. (WH: Petri, Petri-Nets) 

Atlas computer (joint venture between University of Manchester and Ferranti
Ltd.) becomes operational. First machine to use virtual memory and pagin;
instruction execution is pipelined, and the machine contains separate fixed
and floating-point arithmetic units, capable of approximately 200 kFLOPS.
(RNI: Atlas) 

========1964========

Atomic Energy Commission urges manufacturers to look at "radical" machine
structures. This leads to CDC Star-100, TI ASC, and ILLIAC-IV. (MW: AEC,
CDC, TI, ILLIAC-IV) 

Control Data Corporation produces CDC 6600, the world's first commercial
supercomputer. (GVW: CDC, Cray, CDC 6600) 

Air Force signs ILLIAC-IV contract with University of Illinois. The project
is led by Daniel Slotnick; primary subcontractors are Burroughs and Texas
Instruments. (MW: ILLIAC-IV) 

========1965========

Multics project begun by GE, MIT, and AT&T Bell Laboratory, to develop a
general-purpose shared-memory multiprocessing timesharing system. (BM: GE,
MIT, Bell Labs, Multics, symmetric multiprocessing) 

========1966========

Bernstein introduces Bernstein's Condition for statement independence,
which is foundation of subsequent work on data dependency analysis. (GVW:
Bernstein, compilation, data dependency) 

Flynn publishes paper describing architectural taxonomy. (GVW: Flynn, taxonomy)

========1967========

Amdahl publishes paper questioning feasibility of parallel processing; his
argument is later called "Amdahl's Law". (GVW: Amdahl) 

Karp, Miller and Winograd publish paper describing dependence vectors and
loop transformations. (MW: vectorization, loop transformation) 

IBM produces the 360/91 (later model 95) with dynamic instruction
reordering. 20 of these were produced over the next several years; the line
was eventually replaced with the slower Model 85. (MW,HGK: IBM, IBM 360/91)

========1968========

Edsger Dijkstra describes semaphores. (GVW: Dijkstra, semaphore) 

Duane Adams of Stanford University coins the term "dataflow" while
describing graphical models of computation in his Ph.D thesis. (PGW:
dataflow, Stanford University)

Group formed at Control Data to study computing needs for image processing;
this leads to AFP and Cyberplus designs. (MW: CDC, Cyberplus)

IBM 2938 Array Processor delivered to Western Geophysical (who promptly
painted racing stripes on it). First commercial machine to sustain 10
MFLOPS on 32-bit precision. A programmable digital signal processor, it
proves very popular in the petroleum industry. (HGK,GP: IBM, IBM 2938,
array processor)

========1969========

Honeywell delivers first Multics system (symmetric multiprocessor with up
to 8 processors). (BM: Honeywell, Multics, symmetric multiprocessing)

CDC produces CDC 7600 pipelined supercomputer. (GVW: CDC, Cray, CDC 7600)

George Paul, M. Wayne Wilson, and Charles Cree begin work on VECTRAN, an
extension to FORTRAN 66 with array-valued operators, functions, and I/O
facilities. (GP: IBM, FORTRAN, VECTRAN) 

========1970========

Floating Point Systems Inc. founded by former C N Winningstad and Tektronix
employees to manufacture floating-point co-processors for minicomputers.
(GVM,BRC: FPS)

PDP-6/KA10 master/slave (asymmetric) multiprocessor jointly developed by
MIT and DEC. (JMF: DEC, asymmetric multiprocessor) 

Development of C.mmp begins at Carnegie-Mellon. (GVW: C.mmp, CMU) 

========1971========

Edsger Dijkstra poses the dining philisophers problem which is often used
to test the expressivity of new parallel languages. (WH: Dijkstra, dining
philisophers)

Intel produces 4004 microprocessor (world's first single-chip CPU). (GVW: Intel)

CDC delivers hardwired Cyberplus parallel radar image processing system to
Rome Air Development Center, where it produces 250 times the performance of
CDC 6600. (MW: CDC, Cyberplus) 

Texas Instruments delivers the Advanced Scientific Computer (also called
Advanced Seismic Computer). Seven of these machines were developed. An
aggressive automatic vectorizing Fortran compiler was developed for this
machine. (MW: TI, ASC) 

========1972========

Seymour Cray leaves Control Data Corporation, founds Cray Research Inc.
(GVW: CDC, CRI)

Quarter-sized (64 PEs) ILLIAC-IV installed at NASA Ames. (GVW: ILLIAC-IV,
NASA Ames)

BBN builds first Pluribus machines as ARPAnet switch nodes. (GVW: BBN, Pluribus)

Goodyear produces STARAN, a 4X256 1-bit PE array processor using
associative addressing and a FLIP-network. (MCS: Goodyear, Staran) 

Burroughs builds PEPE (Parallel Element Processor Ensemble) with 8X36
processing elements and associative adressing. (MCS: Burroughs, PEPE) 

Paper studies of massive bit-level parallelism done by Stewart Reddaway at
ICL. These later lead to development of ICL DAP. (GVW: ICL, DAP)

TOPS-10 monitor for PDP-10 re-written by DEC to allow asymmetric
multiprocessing. (JMF,PR: DEC, asymmetric multiprocessor) 

========1973========

William Callaghan, working for TI on TI ASC compiler, describes GCD test
for data dependence analysis. (MW: vectorization, GCD test) 

========1974========

Tony Hoare describes monitors. (GVW: Hoare, monitors) 

Jack Dennis and David Misunas at MIT publish first paper describing a
dataflow computer. (PGW: MIT, dataflow)

Leslie Lamport's paper "Parallel Execution of Do-Loops" appears;
theoretical foundation for all later work on automatic vectorization and
shared-memory parallelization. (HZ: Lamport, vectorization) 

IBM 3838 array processor (a general-purpose digital signal processor)
delivered. (HGK: IBM, IBM 3838, array processor) 

Work begins on prototype DAP (Distributed Array Processor) at ICL. (GVW:
ICL, DAP)

Design begins on Burroughs Scientific Processor (BSP). (MW: BSP) 

Burton Smith begins designing context-flow Heterogeneous Element Processor
(HEP) for Denelcor. (GVW: Denelcor, HEP) 

========1975========

Edsger Dijkstra describes guarded commands. (WH: Dijkstra, guarded commands)

ILLIAC-IV becomes operational at NASA Ames after concerted check out
effort. (MW: ILLIAC-IV)

Work begins at Carnegie-Mellon University on Cm*, with support from DEC.
(GVW: CMU, Cm*)

Design of iAPX 432 (symmetric multiprocessor) begins at Intel. (GVW: Intel,
iAPX 432)

Cyber 200 project begins at Control Data. (MW: CDC, Cyber) 

========1976========

Parafrase compiler system developed at University of Illinois under the
direction of David Kuck; this is the successor to a program called the
Analyzer. (MW: vectorization, Kuck, Parafrase) 

U. Banerjee's thesis formalizaes the concept of data dependence, and
describes and implements the analysis algorithm named after him. (MW,HZ:
vectorization, Banerjee)

First Cray-1 delivered to Los Alamos National Laboratory. (MW: CRI, Cray-1)

Borroughs delivers PEPE to BMDATC Advanced Research Center, Huntsville,
Alabama (MCS: Burroughs, PEPE) 

Control Data delivers Flexible Processor, a programmable signal processing
unit. (MW: CDC, Flexible Processor) 

Floating Point Systems Inc. delivers 38-bit AP-120B array processor that
issues multiple pipelined instructions every cycle. (BRC: FPS, array
processor, LIW)

Floating Point Systems Inc. describes loop wrapping, later called software
pipelining, to program pipelined multiple instruction issue processors.
(BRC: FPS, software pipelining, array processor) 

========1977========

Roger Hockney introduces N(1/2) and R(infinity) as metrics for pipelined
and other architectures. (RWH: N(1/2), R(infinity), performance metrics)

C.mmp hardware completed at Carnegie-Mellon University (crossbar connecting
minicomputers to memories). (GVW: CMU, C.mmp) 

Al Davis of the University of Utah, in collaboration with the Burroughs
Corporation, builds the first operational hardware dataflow processor
called the DDM1 (Data-Driven Machine 1). This is based on the static model
of dataflow token scheduling. (PGW: Davis, University of Utah, Burroughs
Corporation, DDM1, static dataflow) 

Massively Parallel Processor project first discussed at NASA for fast image
processing. (MW: Goodyear, MPP)

Defacto standards activity started by the linear algebra community to
define basic vector operations used in linear algebra. The collection is
called the Basic Linear Algebra Subprograms or BLAS. Later the name is
changed to the Level 1 BLAS. Project to develop a portable software package
used to solve systems of linear equation is started, this effort is called
the LINPACK project. (JD: BLAS, standards, LINPACK)

========1978========

Fortune and Wyllie publish paper describing the PRAM model. (GVW: Fortune,
Wyllie, PRAM)

Kung and Leiserson published first paper on systolic arrays. (CEL: systolic arrays)

Leslie Lamport describes algorithm for creating partial order on
distributed events. (GVW: Lamport, virtual time) 

Tony Hoare describes CSP. (WH: Hoare, CSP) 

John Backus (inventor of Fortran) publishes paper on FP systems, arguing
that dependence on conventional languages has made the development and use
of non-von Neumann architectures uneconomical, and has deprived computer
architects of an intellectual foundation for new computers. (PGW: Backus,
FP, dataflow)

Arvind, Kim Gostelow and Wil Plouffe (at the University of California,
Irvine) describe the Unravelling Interpreter (U-Interpreter), which
exploits even greater concurrency than the static dataflow model. This idea
comes to be referred to as the dynamic dataflow model. The dataflow
language Id (Irvine dataflow) is introduced. (PGW: Arvind, Gostelow,
Plouffe, U-Interpreter, dynamic dataflow, Id) 

BBN begins design of distributed-shared memory machine based around
"butterfly" switch, with its roots in work on perfect-shuffle networks by
Stone (1972) and on Omega networks by Lawrie (1975). (GVW, HSS: BBN,
Butterfly)

========1979========

Parviz Kermani and Leonard Kleinrock describe the virtual cut-through
technique for message routing. (GVW: Kermani, Kleinrock, virtual
cut-through, message routing)

Josh Fisher describes a technique called "trace scheduling", a method of
compiling for wide-word machines. This later becomes the foundation for
Multiflow's VLIW systems. (MW: VLIW, trace scheduling) 

ICL DAP delivered to Queen Mary College, London --- world's first
commercial massively parallel computer. (GVW: ICL, DAP) 

Inmos set up by British government to develop and produce memory chips and
microprocessors. (GVW: Inmos)

First single-processor prototype of Denelcor HEP operational. (GVW:
Denelcor, HEP)

The first dataflow multiprocessor (with 32 processors) becomes operational
at CERT-ONERA in Toulouse, France. It is based on the static model and is
known as the LAU system after its programming language (Language en
Assignation Unique). (PGW: dataflow, CERT-ONERA, LAU)

Texas Instruments begins work on the DDP (Data-Driven Processor), based on
the static model, and on a FORTRAN compiler to run on it. (PGW: dataflow,
TI, DDP)

IBM's John Cocke designs the 801, the first of what are later called RISC
architectures. (HGK: IBM, RISC, IBM 801) 

Level 1 BLAS published/released. LINPACK software package complete and
released; the LINPACK Users' Guide finished; the Linpack Users' Guide
contains the first LINPACK Benchmark Report, with 17 machines ranging from
the DEC PDP-10 to the Cray 1 which achieves 4 MFLOPS for a 100^2 matrix at
full precision on a single processor. (JD: BLAS, standards, Linpack
Benchmark, Cray-1)

========1980========

J. T. Schwartz publishes paper describing and analysing the ultracomputer
model, in which processors are connected in a shuffle/exchange graph. (HSS:
Schwartz, ultracomputer) 

Robin Milner, working at Edinburgh, describes the Calculus of Communicating
Systems. (: Milner, CCS)

PFC (Parallel Fortran Compiler) developed at Rice University under the
direction of Ken Kennedy. (MW: PFC, Kennedy, vectorization) 

Teradata spun off from Citibank to develop parallel database query
computers. (GVW: Teradata)

Burroughs Scientific Processor project cancelled after one sale but before
delivery. (MW: BSP)

Mitsui Shipbuilding Company installs a 32-processor ring array called PPA
at Hokkaido University, Japan. (YO: PPA) 

DEC develops KL10 TOPS-10 based symmetric multiprocessor (up to three CPUs
supported, but a customer built a five-CPU system). (JMF: DEC, symmetric
multiprocessor)

========1981========

Franco Preparata and Jean Vuillemin describe the cube-connected cycles
topology. (GVW: Preparata, Vuillemin, cube-connected cycles) 

Paper by Kuck, Kuhn, Padua, Leasure, and Wolfe on use of dependence graphs
for vectorization. (HZ: vectorization) 

Carver Mead gives seminar on massive parallelism at California Institute of
Technology; inspires development of Cosmic Cube hypercube at Caltech by
group led by Charles Seitz (computer science) and Geoffrey Fox (physics).
(GVW: Caltech, hypercube, Seitz, Fox) 

Danny Hillis writes first description of the Connection Machine
architecture (appears as memo from Artificial Intelligence Lab at MIT).
(BMB: TMC, Connection Machine)

First BBN Butterfly delivered --- 68000s connected through multistage
network to disjoint memories, giving appearance of shared memory. (GVW:
BBN, Butterfly)

iAPX 432 prototype completed; Intel abandons project. (GVW: Intel, iAPX 432)

DEC produces VAX 11/782 asymmetric multiprocessor; a small number of
4-processor machines (11/784) are built. (JMF, PR: DEC, VAX, asymmetric
multiprocessor)

Control Data delivers Cyber 205 vector supercomputer. (MW: CDC, Cyber)

The first dynamic dataflow computer becomes operational at the University
of Manchester. (PGW: Manchester, dataflow) 

Floating Point Systems Inc. delivers 64-bit FPS-164 array processor that
issues multiple pipelined instructions every cycle, start of
mini-supercomputer market. (BRC: FPS, FPS-164, array processor, LIW,
mini-supercomputer)

Silicon Graphics Inc. is founded in late 1981, by James H. Clark and others
to develop the IRIS, a high-performance graphics workstation. (DS: Silicon
Graphics, IRIS, Clark)


========1982========

Michael Wolfe's thesis on optimizing compilers for supercomputers (first
detailed, coherent account of program transformations for vectorization and
shared-memory parallelization). (HZ: Wolfe, restructuring compilers,
vectorization)

ILLIAC-IV decommissioned. (GVW: ILLIAC-IV) 

Steve Chen's group at Cray Research produces first X/MP machine (2
pipelined processors with shared memory). (GVW: CRI, Cray-X/MP) 

First Denelcor HEPs installed in US. (GVW: Denelcor, HEP) 

Hitachi introduces S-810/10 and S-810/20 vector supercomputers. (YO: S-810,
Hitachi)

Control Data improves Flexible Processor to make Advanced Flexible
Processor. (MW: CDC, AFP)

{Cosmic Cube hypercube prototype operational at Caltech; first predecessor
of CrOS (Crystalline Operating System) running.} {GVW, {Caltech, hypercube,
MPI}}

Convex founded to pursue mini-supercomputer market. (GVW: Convex) 

Alliant (originally named Dataflow) founded. (GVW,MW: Alliant) 

========1983========

DARPA starts Strategic Computing Initiative, which helps fund such machines
as Thinking Machines Connection Machine, BBN Butterfly, WARP from Carnegie
Mellon University and iWarp from Intel Corp. (MW: DARPA)

Gottlieb and others describe the NYU Ultracomputer, a shared-memory machine
based on a multistage network using message combining. Works begins on
construction of the Ultracomputer at New York University; a related
project, the RP3, is begun at IBM. (AG: message combining, NYU,
Ultracomputer, RP3, IBM)

Full Cosmic Cube hypercube running at Caltech; work begins on Mark II.
Steve Colley and John Palmer (of Intel) sees Caltech machines, and leaves
Intel to found nCUBE. (GVW,VK: Caltech, hypercube, nCUBE) 

Fujitsu ships first VP-200 vector supercomputer. (YO: Fujitsu, VP-200)

NEC introduces SX-1 vector supercomputer. (YO: NEC, SX-1) 

Massively Parallel Processor delivered by Goodyear Aerospace to NASA
Goddard. (MW: Goodyear, MPP)

Loosely-coupled VAXclusters supported by DEC's VMS operating system. (JMF:
DEC, symmetric multiprocessor, VAX) 

Myrias Research founded as spin-off from University of Alberta to build
shared-memory mini-supercomputers. (GVW: Myrias) 

Scientific Computer Systems founded to design and market a Cray-compatible
minisupercomputer. (MW: SCS) 

Sheryl Handler and Danny Hillis found Thinking Machines Corporation; Danny
Hillis' Ph.D. thesis becomes the starting point for a massively-parallel AI
supercomputer. (BMB: TMC) 

ETA Systems, Inc. spun off from CDC to develop a new generation of vector
supercomputers. (GVW: CDC, ETA)

Encore founded. (GVW: Encore)

Sequent founded. Several of its founders are former members of Intel iAPX
432 project. (GVW,TL: Sequent, Intel, iAPX 432) 

Cray-1 with 1 processor achieves 12.5 MFLOPS on 100^2 LINPACK. (JD: Linpack
Benchmark, Cray-1)

J. R. Allen's Ph.D. thesis at Rice University introduces the concepts of
loop-carried and loop-independent dependencies, and formalizes the process
of vectorization. (HZ: data dependence analysis, vectorization)

David May publishes first description of Occam, a concurrent programming
language closely associated with the transputer. (RS: Occam)

Sisal 1.0 (Streams and Iterations in a Single-Assignment Language) language
definition released by Lawrence Livermore National Laboratory (LLNL),
Colorado State University, DEC, and University of Manchester. A derivative
of VAL, the language included array operations, streams, and iterations.
(JF: SISAL, functional languages) 

========1984========

Kurt Mehlhorn and Uzi Vishkin describe how various classes of PRAM can
simulate one another. This work forms the basis for Valiant's later work on
random routing and optimality. (GVW: Mehlhorn, Vishkin, PRAM, emulation)

Ron Cytron's Ph.D. thesis at the University of Illinois introduces concept
of DOACROSS loops. (HZ: Cytron, DOACROSS, vectorization) 

Cydrome founded to build VLIW-style mini-supercomputers with architectural
support for software pipelining of loops. (RR: Cydrome, VLIW)

Sequent produces first shared-memory Balance multiprocessors, using NS32016
microprocessors and proprietary DYNIX symmetric operating system. (GVW,TL:
Sequent, Balance)

Mitsui Shipbuilding Company installs a two-dimensional toroidal array of
processors, PAX-64J, at the University of Tsukuba, Japan. (YO: PAX-64J)

Cray X/MP family expanded to include 1 and 4 processors. (GVW: CRI, Cray-X/MP)

Convex ships prototype version of C1 mini-supercomputer. (DHS: Convex, C1)

Unimpressed with available commercial machines, Caltech begins work on Mark
III hypercube. (GVW: Caltech, hypercube) 

Intel Scientific Computers set up by Justin Rattner to produce commercial
hypercube machines. (GVW: Intel, hypercube) 

Multiflow founded by Fisher and others from Yale to produce very long
instruction word (VLIW) supercomputers. (GVW: Multiflow) 

Cray X/MP with 1 processor achieves 21 MFLOPS on 100^2 LINPACK. (JD:
Linpack Benchmark, Cray X/MP)

========1985========

Dally and Seitz develop model of wormhole routing, invent virtual channels,
and show how to perform deadlock-free routing using virtual channels. (WD:
Dally, Seitz, wormhole routing, virtual channels) 

Leiserson publishes first paper describing fat-tree network. (CEL: fat
trees, message routing)

Pfister and Norton analyse effect of hot spots in multistage networks, and
describe how message combining can ameliorate their effect. (GVW: Pfister,
Norton, hot spots, message combining) 

TMC demonstrates first CM-1 Connection Machine to DARPA. (BMB: TMC, CM-1)

Denelcor closes doors. (GVW: Denelcor)

IBM introduces 3090 vector processor. (HGK: IBM, IBM 3090) 

Intel produces first iPSC/1 hypercube (80286 processors connected through
Ethernet controllers). (GVW: Intel, iPSC/1) 

Inmos produces first (integer) T414 transputer. Members of implementation
group leave to found Meiko, which demonstrates its first transputer-based
Computing Surface at SIGGRAPH that year. ESPRIT Supernode project begun to
produce floating-point transputer. (GVW: Inmos, transputer, Supernode,
Meiko) 

Alliant delivers first FX/8 vector multiprocessor machines using a custom
implementation of an extended Motorola 68020 instruction set. An
auto-parallelizing Fortran compiler is shipped with the machine. (SCP:
Alliant, FX/8)

Fujitsu introduces VP-400 vector supercomputer. (YO: Fujitsu, VP-400) 

First NEC SX-2 vector supercomputer shipped (6.0 ns clock, capable of
producing 8 floating point results per clock cycle, up to 256 MByte
memory). (PDT: NEC, SX-2)

nCUBE produces first nCUBE/10 hypercube using custom processors. (GVW:
nCUBE, nCUBE/10)

Teradata ships first DBC/1012 parallel database query engine (Intel 8086
processors connected by proprietary tree network). (GVW: Teradata,
DBC/1012)

Ring-connected multiprocessor delivered by Control Data, called the
Cyberplus. (MW: CDC, Cyberplus)

Floating Point Systems Inc. delivers FPS-264, an ECL version of 64-bit FPS-164 array processor that issues multiple 
pipelined instructions every cycle. (BRC: FPS, FPS-264, array processor, mini-supercomputer) 

Convex ships first production version of single-processor C1
mini-supercomputer. (MW,DHS: Convex, C1) 

Cray Research produces Cray-2, with four background processors, a single
foreground processor, and a 4.1 nsec clock cycle. (GVW: CRI, Cray-2)

IBM begins RP3 project, intending to build a scalable shared-memory
multiprocessor using a message-combining switch. (HGK: IBM, IBM RP3) 

Stellar Computer, Inc., founded by Bill Poduska, former Apollo Computer
founder, to build single-user high-performance graphics workstations. (MW:
Stellar)

Ardent Computer founded by Allen Michels, former founder of Convergent
Technologies, and Gorden Bell, formerly of DEC, to build machines in
competition with Stellar. (MW: Ardent)

Supertek Computers, Inc. is founded by Mike Fung, former Hewlett Packard
RISC project manager. (GVW: Supertek) 

W. K. Giloi's design chosen as basis for German Suprenum project. (MS:
Suprenum, Giloi)

NEC SX-2 with 1 processor achieves 46 MFLOPS on 100^2 LINPACK. (JD: Linpack
Benchmark, NEC SX-2)

Sisal 1.2 language definition released; language definition does not change
for another seven years. (JF: SISAL, functional languages) 

David Gelernter publishes description of Linda language. Key elements of
this later re-appear as the Linda parallel programming system. (GVW:
Gelernter, Linda)

Robert Halstead introudces futures in a paper describing the implementation
of Multilisp. (GVW: Multilisp, Halstead, futures) 

David Jefferson describes how virtual time and time warping can be used as
a basis for speculative distributed simulations. (GVW: Jefferson, timewarp,
simulation)

========1986========

Dally shows that low-dimensional k-ary n-cubes are more wire-efficient than
hypercubes for typical values of network bisection, message length, and
module pinout. Dally demonstrates the torus routing chip, the first
low-dimensional wormhole routing component. (WD: Dally, k-ary n-cubes,
hypercubes, wormhole routing) 

Kai Li describes system for emulated shared virtual memory. (GVW: Li,
shared virtual memory)

Encore ships first bus-based Multimax computer (NS32032 processors coupled
with Weitek floating-point accelerators). (GVW: Encore, Multimax)

Thinking Machines Corp. ships first Connection Machine CM-1 (up to 65536
single-bit processors connected in hypercube). (GVW: TMC, CM-1) 

Scientific Computer Systems delivers first SCS-40, a Cray-compatible
minisupercomputer. (GVW: SCS)

GE installs a prototype 10 processor Warp system at CMU (programmable
bit-slice VLIW systolic array). (JRR: CMU, GE, Warp) 

Cray X/MP with 4 processors achieves 713 MFLOPS (against a peak of 840) on
1000^2 LINPACK. (JD: Linpack Benchmark, Cray X/MP) 

Floating Point Systems introduces T-series hypercube (Weitek floating-point
units coupled to transputers), and ships 128-processor system to Los
Alamos. (BRC: FPS, T-series, transputer) 

Henry Burkhardt, former Data General and Encore founder,        forms
Kendall Square Research Corporation (KSR) to build custom multiprocessor.
(GVW: KSR)

BBN forms Advanced Computers Inc. subsidiary (BBN ACI) to develop and
market Butterfly machines. (GVW: BBN)

Active Memory Technology spun off from ICL to develop DAP products. (GVW:
AMT, ICL, DAP)

Level 2 BLAS activity started. (JD: Level 2 BLAS) 

CrOS III, Cubix (file-system handler) and Plotix (graphics handler) running
on Caltech hypercubes. (GVW: hypercube, MPI) 

Symmetric multiprocessing supported by VMS. (JMF: DEC, symmetric
multiprocessor, VAX)

Alan Karp offers $100 prize to first person to demonstrate speedup of 200
or more on general purpose parallel processor. Brenner, Gustafson, and
Montry begin work to win it, and later win the Gordon Bell Prize. (AK: Karp
Prize)

========1987========

J. van Leuwen and R. B. Tan describe interval routing, a compact way of
encoding distributed routing information for many topologies. This is later
used in the Inmos T9000 transputer. (ER: interval routing) 

Charles Koelbel, Piyush Mehrotra and John Van Rosendale describe Blaze, the
first language to propose a notation for explicit data distribution. (HZ:
Blaze, data distribution) 

ETA produces first air- and liquid nitrogen-cooled versions of ETA-10
multiprocessor supercomputer. (GVW: ETA) 

Myrias produces prototype (68000-based) SPS-1. (GVW: Myrias, SPS-1) 

Caltech Mark III hypercube completed (68020 with wormhole routing). (GVW:
Caltech, hypercube)

Cydrome delivers first Cydra 5 system in September. System is a
multi-processor, with a single VLIW-style numeric processor for numeric
applications, plus multiple scalar processors for I/O and other
general-purpose processing. Numeric processor has a 256-bit instruction
word capable of 7 operations per cycle. (RR: Cydrome, VLIW)

TMC introduces CM-2 Connection Machine (64k single-bit processors connected
in hypercube, plus 2048 Weitek floating point units). (GVW: TMC, CM-2)

Sequent produces 80386-based Symmetry bus-based multiprocessor. (GVW,TL:
Sequent, Symmetry)

Multiflow delivers first Trace/200 VLIW machines (256 to 1024 bits per
instruction). (GVW: Multiflow, Trace/200) 

GE installs the first 10-processor production Warp system at CMU. (JRR:
CMU, GE, Warp)

Seitz, working at Ametek, builds the Ametek-2010, the first parallel
computer using a 2-D mesh interconnect with wormhole routing. (WD: Seitz,
Ametek, Ametek-2010, wormhole routing) 

Steve Chen leaves Cray Research to found Supercomputer Systems, Inc. SSI is
later funded by IBM to build large-scale parallel supercomputer. (MW: CRI,
SSI)

Gordon Bell Prize for parallel performance first awarded; recipients are
Brenner, Gustafson, and Montry, for a speedup of 400-600 on variety of
applications running on a 1024-node nCUBE; and Chen, DeBenedictis, Fox, Li,