Re: Vyatta as a BRAS

["Christian Chapman" <christianchapman () eircom net>]

> > Sorry, it's software running those ASIC's and FPGA's, even at that level
Sorry ..Its a clock that runs ASIC's and FPGA's
HDL is simply used to describe functionality before synthesis tools 
translate the design into real hardware (gates and wires)



----- Original Message ----- 
From: "Lamar Owen" <lowen () pari edu>
To: <nanog () nanog org>
Sent: Tuesday, July 13, 2010 10:25 PM
Subject: Re: Vyatta as a BRAS


> On Tuesday, July 13, 2010 11:11:57 am Greg Whynott wrote:
> > > They are all software based, no matter who builds them.  Cisco IOS,
> > > Juniper JunOS, etc.
> >
> > controlling hardware asic's and fpga's.
>
> That run low level software microcode and bitstreams.  Sorry, it's 
> software running those ASIC's and FPGA's, even at that level.  Verilog and 
> VHDL, while not your ordinary programming languages, blur the line very 
> effectively.