nanog mailing list archives
Re: T1 Circuit actual throughput 1290Kbps
From: "Robert E. Seastrom" <rs () bifrost seastrom com>
Date: Thu, 9 Jul 1998 11:05:15 -0400 (EDT)
From: "Robert E. Seastrom" <rs () bifrost seastrom com> Precisely. The most likely explanation is that the T1 is actually D4 framed, uh, my wrong... it's the AMI not the D4 that causes the big hit. of course, as a matter of course, D4/AMI and ESF/B8ZS go together and you never see combinations like D4/B8ZS... which, in answer to the fellow who asked, is why you can't just invert the data on the HDLC and run it down the line and get your 12% back... HDLC is layer 2, whilst framing is layer 1... ---Rob
Current thread:
- Re: T1 Circuit actual throughput 1290Kbps, (continued)
- Re: T1 Circuit actual throughput 1290Kbps Patrick W. Gilmore (Jul 08)
- Re: T1 Circuit actual throughput 1290Kbps Jose Dominguez (Jul 09)
- Re: T1 Circuit actual throughput 1290Kbps Vincent Poy (Jul 10)
- Re: T1 Circuit actual throughput 1290Kbps Mark Milhollan (Jul 10)
- Re: T1 Circuit actual throughput 1290Kbps James Carlson (Jul 10)
- Re: T1 Circuit actual throughput 1290Kbps Jose Dominguez (Jul 09)
- Re: T1 Circuit actual throughput 1290Kbps Nathan Stratton (Jul 08)
- Re: T1 Circuit actual throughput 1290Kbps Lincoln Dale (Jul 08)
- Re: T1 Circuit actual throughput 1290Kbps Dorian Kim (Jul 08)
- Re: T1 Circuit actual throughput 1290Kbps Brett Frankenberger (Jul 09)
- Re: T1 Circuit actual throughput 1290Kbps Robert E. Seastrom (Jul 09)
- Re: T1 Circuit actual throughput 1290Kbps Robert E. Seastrom (Jul 09)
- Re: T1 Circuit actual throughput 1290Kbps Brett Frankenberger (Jul 12)
- Re: T1 Circuit actual throughput 1290Kbps Dorian Kim (Jul 08)
- Re: T1 Circuit actual throughput 1290Kbps Patrick W. Gilmore (Jul 08)
- Re: T1 Circuit actual throughput 1290Kbps James Carlson (Jul 09)