HOT CHIPS SYMPOSIUM VII ADVANCE PROGRAM AUGUST 13-15, 1995

[David Farber <farber () central cis upenn edu>]

          Just When You Thought It Was Safe To Go On Vacation


                        HOT CHIPS SYMPOSIUM VII
                 A Symposium on High-Performance Chips
                           (Advance Program)


                 Sponsored by the IEEE Computer Society
                 Technical Committee on Microprocessors


                 Stanford University, Stanford, California
                          Memorial Auditorium
                           August 13-15, 1995


Attend HOT Chips VII, a symposium on high-performance chips, which will
bring together researchers and developers of chips used to construct
high-performance workstations and systems.  Enjoy the informal format
offering interaction with speakers.  The first six HOT Chips Symposiums
were huge successes and prompted articles in special issues of IEEE
Micro magazine.


Since 1989, Hot Chips has attracted an audience of pioneers in the
computer field as well as the hottest young designers.  Each year, Hot
Chips has presented the latest developments in microprocessors, graphic
chips, support chips, compression chips, and embedded processors.  Join
us also on Sunday for two tutorials and bring yourself up-to-date on
the state of the art in graphics and the X86 architectures.


You'll receive a notebook with all of the presentation slides,
delicious meals on the beautiful Stanford campus, and we'll even
provide parking!




ORGANIZING COMMITTEE:


General Chairman:               Nam Ling, Santa Clara University
Vice Chairman:                  Martin Freeman, Philips Research
Program Co-Chairmen:            Hasan S. AlKhatib, Santa Clara University
                                Norman P. Jouppi, Digital Equipment Corp.
Finance Chairman:               Dennis Reinhardt, Intel Corporation
Publication Chairman:           David Gustavson, SCIzzL
Registration Chairman:          Robert Stewart, Stewart Research Enterprises
Publicity Chairmen:             Weijia Shang, Santa Clara University
                                S. Diane Smith, Consultant
World Wide Web Chairmen:        Fuyau Lin, Santa Clara University
                                Robert Stewart, Stewart Research Enterprises
Local Arrangements Chairmen:    Alan Johnson
                                Cary Kornfeld, KDL
Tutorials Chairman:             Qiang Li, Santa Clara University
At Large:                       John Hennessy, Stanford University
                                John Mashey, Silicon Graphics


PROGRAM COMMITTEE


Hasan S. AlKhatib, Santa Clara University (Program Co-Chairman)
Donald Alpert, Intel Corporation
Forest Baskett, Silicon Graphics
Robert Garner, Sun Microsystems
Mark Horowitz, Stanford University
Norman P. Jouppi, Digital Equipment Corp. (Program Co-Chairman)
Vivian Shen, Hewlett Packard
Shanker Singh, IBM
Alan Jay Smith, UC Berkeley
Winfried W. Wilcke, HaL Computer Systems




This is a preliminary program. Presentations may be dropped, added
and/or moved between sessions. Session times may change.


Check the World Wide Web for Program Updates:
http://dice.scu.edu/HotChips or http://www.hot.org/hotchips


HOT Chips VII is sponsored by the Technical Committee on
Microprocessors and Microcomputers of the IEEE Computer Society.




PROGRAM


SUNDAY, August 13, 1995 - Memorial Auditorium


Sunday Tutorial Schedule


 7:30 -  8:30  Registration & Coffee at Memorial Auditorium
 8:30 - 12:00  Silicon Parts for Computer Graphics?
12:00 -  1:00  Lunch
 1:00 -  4:30  x86 Generations: Past, Present & Future
 4:30 -  6:00  Wine & Cheese Reception in the Dohrmann Grove
               just north of the Hoover Tower on Serra Street.




MORNING TUTORIAL: Silicon Parts for Computer Graphics?


Frank Crow, Interval Research


A quick tutorial on computer graphics with emphasis on realistic 3D scenes
and the requirements for real-time interaction with computed imagery will be
presented.


  * Scan conversion - geometry to pixels, antialiasing
  * The traditional graphics pipeline
  * Shading and lighting
  * Texturing schemes
  * Ray tracing as an alternative to the traditional pipeline
  * Real-time graphics, immersion, latency issues


Architectural approaches to accelerating graphics will be surveyed,
illustrated by case studies from existing and proposed designs.


  * Bandwidth issues in the traditional pipeline
  * Scan conversion acceleration, geometry acceleration
  * Frame buffer designs; VRAM vs. DRAM vs. ?; interleaving; caching?
  * Rich shading and texturing vs. millions of polygons
  * Features ripe for acceleration?


We hope to get some input from multi-media, games, and other content
developers on their desires for hotter graphics.  The overall intent is to
leave attendees with a level of understanding that will encourage further
exploration and promote intelligent discussions of what silicon parts, if
any, should be built specifically to accelerate graphics in the near future.


AFTERNOON TUTORIAL: x86 Generations: Past, Present & Future


John H. Wharton, Applications Research


The verdict is in: even the most die-hard critics of CISC philosophy
are starting to concede that the x86 architecture may be around for a
while.  Pentium is arguably the fastest 32-bit processor ever to evolve
from a custom eight-bit CRT controller. Evolution can be tricky; for
each new, desirable feature the x86 family acquired as it grew there's
a vestigial appendage that was faithfully reproduced. The first half of
this tutorial gives a historical perspective of the features - good,
bad, and ugly - that make x86 processors so special; reviews the
evolution of the Intel product line, with an emphasis on the 486 and
Pentium generations; and gives a survey of competing designs from AMD,
Cyrix, and NexGen. The second half of the tutorial is devoted to the
next-generation "P6". We will describe what's known about the P6
microarchitecture, bus protocols, and system design issues, and will
conclude by speculating on a number of intriguing unknowns.




MONDAY, August 14, 1995 - Memorial Auditorium


9:00-9:15       Welcome and Opening Remarks
                Nam Ling, General Chair
                Hasan S. AlKhatib and Norman P. Jouppi, Program Co-Chairs


9:15-10:45      SESSION 1: EMBEDDED PROCESSORS
                Session Chair:  Robert Garner, Sun Microsystems


*  The First Superscalar 29K Family Member
   B. McMinn, Advanced Micro Devices


*  The Architecture of the NS486 Integrated Processor
   M. D. Nemirovsky, National Semiconductor


*  Superscalar MIPS-II Microprocessor for Core-Based ASIC
   P. Cobb, J. Cesana, LSI Logic


10:45-11:15     BREAK


11:15-12:15     KEYNOTE ADDRESS: "Nanometers and Gigabucks"
                Gordon Moore, Chairman of Intel Corporation


12:15-1:45      LUNCH


1:45-3:15       SESSION 2: x86 PROCESSORS
                Session Chair:  Mark Horowitz, Stanford University


*  The Impact of Dynamic Execution Techniques on the Data Path Design
   of the P6 Processor
   D. Papworth, Intel Corporation


*  The AMD K5 Processor
   D. Christie, Advanced Micro Devices


*  Building a Better Beast: Native vs. RISC-Like vs. VLIW Implementations
   of x86 Processors
   T. Garibay, Cyrix


3:15-3:45       BREAK


3:45-5:15       SESSION 3: RISC-1
                Session Chair:  Winfried W. Wilcke, HaL Computer Systems


*  Performance Evaluation of the Superscalar, Speculative
   Execution HaL SPARC64 Processor
   A. Essen, S. Goldstein, HaL Computer Systems


*  SPARC64+: HaL's Second Generation 64-bit SPARC Processor
   G. W. Shen, HaL Computer Systems


*  Memory Performance Features of the 64-bit PA-8000
   B. Naas, Hewlett-Packard


5:15-7:00       BUFFET DINNER


7:00-9:00       EVENING PANEL SESSION


                Is There a Role for Competing Architectures in an x86 World?
                Moderator:  John H. Wharton, Applications Research




TUESDAY, August 15, 1995 - Memorial Auditorium


9:00-10:30      SESSION 4: MPEG
                Session Chair:  Vivian Shen, Hewlett-Packard


*  A Two-Chip Realtime MPEG2 Video Encoder with Wide Range Estimation
   T. Kondo, K. Suguri, M. Ikeda, T. Abe, H. Matsuda, T. Okubo,
   K. Ogura, Y. Tashiro, NTT LSI Laboratories


*  VLSI Architecture of the I-Frame Encoder
   for the MPEG-2 Video Compression
   A. Ngai, IBM


*  A Scenic View
   C. Stearns, S3 Inc.


10:30-11:00     BREAK


11:00-12:30     SESSION 5: GRAPHICS AND COMPRESSION
                Session Chair:  Shanker Singh, IBM


*  3D Graphics Processor Chip Set
   M. Agawa, Fujitsu Limited


*  A Single Chip VideoCD with Hi-Fi Audio
   for Consumer Applications
   J. Fandrianto, B. Martin, Integrated Information Technology


*  Highly Reliable and Low-CPB IBMLZ1 Compression
   Algorithm and Technology for Storage Controller
   J. M. Cheng, L. M. Duyanovich, IBM


12:30-2:00      LUNCH


2:00-4:00       SESSION 6: PARALLEL AND VECTOR PROCESSING
                Session Chair:  Alan Jay Smith, UC Berkeley


*  Breakthroughs in Parallelizing Compilers and
   Their Architectural Implications
   S. P. Amarasinghe, J. A. M. Anderson, R. S. French, M. W. Hall,
   M. S. Lam, S. W. Liao, B. R. Murphy, C. W. Tseng, C. S. Wilson,
   R. P. Wilson, Stanford University


*  Scylla: A Memory Controller with Integrated Protocol Engines for
   Distributed Shared Memory Support
   A. Nowatzyk, G. Aybay, M. Browne, B. Radke, S. Vishin, Sun Microsystems


*  The T0 Vector Microprocessor
   K. Asanovic, J. Beck, B. Irissou, D. Kingsbury, N. Morgan,
   J. Wawrzynek, UC Berkeley


*  A 150 MHz Superscalar RISC Processor with
   Pseudo Vector Processing Feature
   K. Saito, M. Hashimoto, K. Matsubara, H. Sawamoto, R. Yamagata, T. Kumagai,
   E. Kamada, T. Hotta, T. Nakano, T. Isobe, Hitachi, Ltd., Hitachi Computer
   Engineering Co., Ltd.;  K. Nakazawa, University of Tsukuba


4:00-4:30       BREAK


4:30-6:30       SESSION 7: RISC-2
                Session Chair:  Donald Alpert, Intel Corporation


*  UltraSPARC-I: A 64-bit Superscalar Processor with Multi-Media Support
   M. Tremblay, Sun Microsystems


*  The First PowerPC PDA Microprocessor
   D. Shamir, Y. Rudin, Motorola


*  Smaller, Faster, Cooler ... Evolving the PowerPC Family
   D. Balser, Somerset PowerPC Design Center, IBM


*  MIPS R10000 Superscalar Microprocessor
   A. Ahi, A. Bomdica, G. Shippen, H. Sucar, H. Su, J. Chuang, N. Vasseghi, R.
   Ramchandani, R. Martin, R. Conrad, Y. Chen, K. Yeager, W. Voegtli Jr., M.
   Seddighnezhad, Y. Van Atta, Silicon Graphics


6:30            CLOSING REMARKS




HOUSING INFORMATION


Housing is available on the Stanford University campus in student
dormatories which are vacant in the summer. These have central lavatory
facilities and cost about $40 per night --- single, $50 per night ---
double, for the nights of the symposium. A key deposit of $50 is
required that will be refunded at checkout.


Please note that Stanford has a very restrictive non-smoking policy
that is strictly enforced in on-campus housing. You can book directly
with Stanford by calling (415) 725-1429 or using Email:
HF.EZB () forsythe stanford edu. Or, you can book Stanford Housing with
HOT Chips on the registration form. If you book with HOT Chips, include
your housing fees in your total registration count.


Housing is also available at numerous hotels and motels on the
peninsula in Palo Alto, Menlo Park, Mountain View, and Los Altos within
5 miles of the campus. You are responsible for making such reservations
directly with the motel.


If you would like additional housing information, please check the
housing information request box on the registration form.


IEEE/Computer Society Membership


To join call Sheri Winter at (202) 371-0101. With confirmation, you may
register for HOT Chips VII at member rates. Half year rates: IEEE
Computer Society --- $68. Membership includes Computer magazine and
Spectrum. Computer Society alone ---$32.




QUESTIONS?


For more information on registration and local arrangements contact Dr.
Robert Stewart at (415) 941-6699 or r.stewart () hot org.




REGISTRATION INCLUDES:


* Attendance                       * Sunday Evening Wine &
* One Copy of the Notes              Cheese Reception
* Two Luncheons                    * Monday Evening Reception
* Coffee Breaks                    * Parking


A Stanford map, parking permit, the location of parking, and a receipt
will be mailed to early registrants.


ON-SITE REGISTRATION is available Sunday morning before the tutorial
and each morning at the Symposium.  Early advanced registration is
recommended because of the large attendance.


Group discounts are available. Life members, retired members, and
unemployed, call Hot Chips for discount information and special rates,
(415) 941-6699.


Use certified mail for registration confirmation.


CANCELLATION OF REGISTRATION: Must be made in writing prior to Sunday,
August 6, 1995. A $25 fee will be charged for cancellation.


FEDERAL TAX ID NUMBER IS: 13-1656633 for the


Institute of Electrical & Electronic Engineers
345 E. 47th Street
New York, NY  10017


Use certified mail for registration confirmation.


=============================================================================




                      HOT CHIPS VII REGISTRATION FORM




Name________________________________________________________________________


Organization________________________________________________________________


Dept/Mail Stop______________________________________________________________


Mailing Address_____________________________________________________________


City/State/Zip______________________________________________________________


Country_____________________________________________________________________


Area Code/Phone #___________________________________________________________


Email Address_______________________________________________________________


FAX_________________________________________________________________________


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                  Student______          None______


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Check One:


______Check drawn on a U.S. Bank                    ______MasterCard
      Make Check Payable To:
      Hot Chips Symposium                           ______VISA


Name on Credit Card_________________________________________________________


Credit Card #_______________________________________________________________


Expiration Date_____________________________________________________________


Signature___________________________________________________________________






FEES: CIRCLE APPROPRIATE VALUES


                             Before July 24         After July 24


IEEE/Computer Society            $160                   $230
or ACM Member


Non-Member                       $230                   $290


Student Member, Full Time        $55                    $100




Sunday Tutorials, Member         $30                    $45


Tutorials, Non-Member            $45                    $60


Tutorials, Student               $20                    $30




Extra Copy of Notebook           $30                    $30
(with no mailing)




Stanford University Dormitory Housing
______ nights @$40 per night single; $50 double $_________


Arrival__________________  Departure___________________






TOTAL AMOUNT PAID               ______________






Electronic Registration, paid via VISA or Mastercard Registration:


By FAX:


FAX:    (415) 941-5048


By Email:


EMAIL:  r.stewart () hot org


By World Wide Web:


Send filled out online form accessed from WWW URL:
http://www.hot.org/hotchips


Surface Mail Registration To:


                        Dr. Robert G. Stewart
                        Stewart Research Enterprises
                        1658 Belvoir Drive
                        Los Altos, CA  94024






Do NOT put me on the Hot Chips Mailing List                    _____


Stanford University Housing Information Requested              _____