AMD's K5 at the uP Forum

[David Farber <farber () central cis upenn edu>]

Date: Thu, 20 Oct 1994 15:23:25 -0700
From: Bruce R Koball <bkoball () well sf ca us>


Dave,


Share this with your list if you think it's appropriate .


------


I just spent the last three days (17-19 Oct 1994) at the 7th annual
Microprocessor Forum, in Burlingame CA. This event is sponsored by
Michael Slater's MicroDesign Resources, the publisher of the
Microprocessor Report. It has become the premiere venue for technical
discussions of microprocessor technologies and typically draws most of
the leading computer architects in the industry (OK, so this is a
shameless plug 'cause I'm on the Editorial Board).


There were at least half a dozen significant new chips announced or
discussed at the Forum, but arguably the most important announcement
was the AMD K5 device. This new chip is interesting for a number of
reasons and may have an impact that will be felt throughout the PC
market.


The K5 is an x86 family device (i.e., it runs DOS/Windows) with
sustained performance 30% higher than Intel's leading-edge x86 family
part, the Pentium. While this is not a quantum leap, it does mark the
first time that Intel has had competition at the high-performance end
of its bread-and-butter market for x86 processors.  Historically, AMD
and all the other alternate x86 vendors, at best, have been able to
offer parts that are one generation behind Intel's lead parts (i.e.,
offering 386 parts while Intel pushed 486, etc...). This competition
will certainly put pressure on high-performance processor prices.


Perhaps even more significant is the way AMD achieved this performance.
While the K5 executes the x86 instruction set, it does so by translating
each x86 instruction into one or more "ROPs" (RISC operations) at
instruction fetch time and then executing them on a sophisticated
four-issue, superscalar RISC processor core, using advanced RISC techniques
like register renaming and speculative, out-of-order execution.


I won't bore you with a recounting of the CISC-RISC religious wars, but
suffice it to say that there is general agreement the CISC architecture
of traditional x86 processors is a severe limitation on the continuing
increased performance of these devices and that RISC machines are the
wave of the future. The realization of a high-performance RISC in x86
clothing points the way around the x86 family's limitation and
seriously threatens the ability of other RISC architectures (Power PC,
SPARC, MIPS) to make a dent in the x86 juggernaut's strangle hold on
the PC market.


Why?...  Because the x86's grip on the PC market is based on the
billion-dollar installed base of x86(i.e., DOS/Windows)-based software
and the main hope of overcoming this enormous advantage that any
competing architecture might have is to provide significantly higher
performance that x86 could't match. Indeed, the x86 architecture is
widely distained and would have been abandoned long ago were it not for
this huge software base.


To be sure, CISC-on-a-RISC is not a new idea. Intel's next-generation
successor to the Pentium (code-named the P6) has been rumored to use
exactly these techniques. The real significance in this announcement is
that there now seems to be a clear path to continued dominance by x86
hardware and software in an announced product.


This is not to say that the rest of the competition will evaporate, but
it does seem that the Power PC's (i.e., mainly Macintosh) market share
will not be growing by leaps and bounds, and that the workstation
architectures (MIPS, SPARC, etc.) will not invade the desktop market to
any significant degree.




Bruce R. Koball         B. R. Koball, Inc.   (voice)    510 845-1350
bkoball () well sf ca us   2210 Sixth St        (messages) 510 548-2450
"No Compromised Keys!"  Berkeley, CA 94710   (fax)      510 845-3946